1. Field of the Invention
The present invention relates to an image sensor, and more particularly, to a method for fabricating a CMOS image sensor suitable for decreasing a dark current.
2. Discussion of the Related Art
Generally, a CMOS image sensor is suitable for a SoC (System on Chip). As the CMOS image sensor is scaled down to a deep sub micron below 0.18 μm, the CMOS image sensor has more competitive power than CCD.
With the demands for a technology of the CMOS image sensor below 0.18 μm, the CMOS image sensor has the various problems in fabrication of pixel array, for example, the limit in size of pixel, the non-silicide process, and the uniformity of color filter array.
Among the various problems, the non-silicide (NASL) process is an essential element for a pixel since it has the great effects on a dark current. Also, the technology of the CMOS image sensor is developed to a high-integration design below 0.18 μm. Accordingly, it is very important to control the non-silicide process.
FIG. 1 is a circuit diagram of showing a unit pixel of a 4-T (transistor) CMOS image sensor according to the related art. FIG. 2 is a layout of showing a unit pixel of a CMOS image sensor according to the related art.
As shown in the drawings, a unit pixel of a 4-T CMOS image sensor is comprised of one photodiode PD and four transistors. The four transistors are formed of a transfer transistor Tx, a reset transistor Rx, a drive transistor Dx and a select transistor Sx. At this time, the transfer transistor Tx transfers optical charges generated in the photodiode PD to a floating diffusion area (FD). The reset transistor Rx sets the electric potential of the floating diffusion area at the predetermined value, and discharges the optical charges to reset the floating diffusion area. Also, the drive transistor Dx functions as a source follow buffer amplifier, and the select transistor Sx is provided for switching and addressing. In addition, a load transistor is provided outside the unit pixel, to read output signals.
In the area of forming the transistors, a silicide layer is formed to improve the speed of the transistors Tx, Rx, Dx and Sx by decreasing a parasitic resistance. However, in case of the photodiode area PD, the silicide layer is not formed due to the optical sensing and dark current leakage. Accordingly, the silicide process is progressed in state of covering the photodiode area with a silicide blocking mask as shown in FIG. 2.
Hereinafter, a method for fabricating a CMOS image sensor according to the related art will be described with reference to the accompanying drawings.
FIG. 3A to FIG. 3F are cross sectional views of showing the process for fabricating a CMOS image sensor according to the related art, which mainly show a photodiode area PD and an adjacent transfer transistor Tx.
First, as shown in FIG. 3A, a photodiode area PD is formed in a semiconductor substrate 11, and a plurality of gates are formed on the semiconductor substrate 11 by interposing a gate oxide layer. The plurality of gates are formed in a transfer transistor Tx, a reset transistor Rx, a drive transistor Dx and a select transistor Sx. At this time, one side of the gate 12 in the transfer transistor Tx is aligned to the edge of the photodiode area PD.
After that, a TEOS layer 13 is formed on an entire surface of the semiconductor substrate 11 including the gate 12. Subsequently, as shown in FIG. 3B, a nitride layer 14 is formed on the TEOS layer 13. Then, as shown in FIG. 3C, a spacer 14a is formed by etching-back the nitride layer 14.
Next, as shown in FIG. 3D, a TEOS layer 15 is formed on the entire surface of the semiconductor substrate 11, wherein the TEOS layer 15 functions as a silicide blocking layer. Then, as shown in FIG. 3E, a photoresist PR is coated on the TEOS layer 15 for the silicide blocking layer, and is then patterned to remain on the photodiode area PD by exposure and development. At this time, the photoresist PR is larger at a range of ‘W’ than the photodiode area PD, in due consideration of the layout margin of wet-etching process.
Subsequently, as shown in FIG. 3F, the TEOS layer 15 is wet-etched in state of using the patterned photoresist PR as a mask, thereby forming the silicide blocking layer 15a. 
Although not shown, the silicide blocking layer 15a has a tapered edge profile due to the wet-etching process, the isotropic etching process. The silicide blocking layer 15a of the tapered edge profile has the problem in that it can not perform the blocking function in the silicide process.
The silicide blocking layer 15a is formed by the wet-etching process. The wet-etching process is advantageous in that it can decrease the surface damage of silicon. However, in case of the wet-etching process, it is difficult to control the process. Also, with the scale-down on chip, it is impossible to obtain the uniform chip efficiency.
FIG. 4 is a graph of measuring a dark current by an integration time of the CMOS image sensor according to the related art, in which a high dark current level is shown.
FIG. 5A, FIG. 5B and FIG. 5C are capture images when having an integration time of 1 ms, 20 ms and 100 ms in the CMOS image sensor according to the related art. In this case, a micro white defect is serious, so that it is difficult to recognize the image after the long integration time.
As the integration time increases, more pairs of electron and hole are generated. That is, the image becomes brighter, whereby it is difficult to recognize the image after the integration time.
FIG. 6A and FIG. 6B are SEM photographs of the CMOS image sensor according to the related art. As shown in FIG. 6A and FIG. 6B, the photodiode area PD is not covered with the silicide blocking layer 15a since the silicide blocking layer 15a has the tapered edge profile. Accordingly, the defects may be generated in the edge of the photodiode area PD and the edge of the spacer adjacent to the photodiode area PD by stress.